GLOSSARY

Industry Acronyms

TitleDescription
CMOS

Complementary Metal Oxide Semiconductor 

I/OInput/Output
IP

Intellectual Property

RAMRandom Access Memory
RTLRegister Transfer Level

Industry Terms

TitleDescription
AVTS(ASIC Verification Test Suite) - set of firmware/software which is designed to test the specified functionality of an SOC. This term may refer to the source code, the object code, or any intermediate form of this code
BlockSource code describing a specific functional implementation
Bus

A set of signals that are grouped together to enable information flow between two or more devices

ChannelA DMA channel in an SOC. An intelligent burst device which transfers data between shared memory and another SOC device. Note: A channel can include intelligent devices which access memory without effecting data transfer, and may include devices which transfer data from one portion of shared memory to another
CoreA complete IP deliverable, including block, and related software and testbenches
CoreFrame® ArchitectureThe architecture, patented by Palmchip, consisting of a high performance, point-to-point interconnection scheme for the easy integration of IP into an SOC. It is foundry, I/O and processor independent, and supports 8-,16-,32- and 64-bit peripherals
CoresComplex, pre-designed function that will be integrated onto a larger chip.*
DMADirect Memory Access) - method by which data is read or written from shared memory by hardware proxy. This may be initiated by firmware, or performed automatically
HAL(Hardware Abstraction Layer) - firmware which provides a semi-or fully standardized interface between an SOC and code designed to exercise the SOC. This code forms a layer between the hardware and software, allowing any software which uses a HAL to be more easily ported to operate with a different SOC. This may or may not include boot code
HALL(Hardware Abstraction Layer Library) - collection of firmware which forms the HAL. The library may include macros, definitions, assembly code, high-level language functions, and other software structures
Hardware ArchitectureConfiguration of all physical elements for meeting a system's objective.*
Hardware/Software Co-DesignDesign methodology supporting the concurrent development of hardware and software to achieve system functionality and performance goals. Often refers to design activities prior to the portioning into hardware and software, and the activity of the design portioning itself.*
Hardware/Software Co-SimulationProcess by which the software is verified against a simulated representation of the hardware prior to the lab or system integration.*
Hardware/Software Co-VerificationAll verification activities for mixed hardware and software systems which occur after the explicit partitioning into hardware and software components, and which involves an explicit representation of both hardware and software elements. Involves both formal and simulation-based techniques and methodologies. Also encompasses the verification activities that use integrated lab system prototypes.*
IP (Intellectual Property) Technologythat can be licensed to enable the creation of an SOC. Palmchip IP may include source code for creation of hardware or software, compiled code, and implementation instructions.*
MC (Memory Controller)

A device that controls shared memory; This device accepts requests for memory access from one or more Channels

SLI

System Level Integration

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